.comment-link {margin-left:.6em;}

2Physics Quote:
"About 200 femtoseconds after you started reading this line, the first step in actually seeing it took place. In the very first step of vision, the retinal chromophores in the rhodopsin proteins in your eyes were photo-excited and then driven through a conical intersection to form a trans isomer [1]. The conical intersection is the crucial part of the machinery that allows such ultrafast energy flow. Conical intersections (CIs) are the crossing points between two or more potential energy surfaces."
-- Adi Natan, Matthew R Ware, Vaibhav S. Prabhudesai, Uri Lev, Barry D. Bruner, Oded Heber, Philip H Bucksbaum
(Read Full Article: "Demonstration of Light Induced Conical Intersections in Diatomic Molecules" )

Sunday, January 05, 2014

Carbon Nanotube Computer

H.-S. Philip Wong (left) & Subhasish Mitra (right) led the team of researchers that developed the carbon nanotube computer

Authors:
Max M. Shulaker1, Gage Hills1, Nishant Patil1, Hai Wei1, Hong-Yu Chen1
H.-S. Philip Wong1, and Subhasish Mitra1,2

Affiliation:
1Department of Electrical Engineering, Stanford University, USA
2Department of Computer Science, Stanford University, USA

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy–delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies [1,2].

Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems [3, 4].

Since the initial discovery of CNTs, there have been several major milestones for CNT technologies [6]: Carbon nanotube field effect transistors (CNFETs), basic circuit elements (logic gates), a five-stage ring oscillator fabricated along a single CNT, a percolation-transport-based decoder, stand-alone circuit elements such as half-adder sum generators and D-latches, and a capacitive sensor interface circuit [7, 8, 9, 10, 11, 12, 13]. Yet there remains a serious gap between these circuit demonstrations for this emerging technology and the first computers built using silicon transistors, such as the Intel 4004 and the VAX-11 (1970s). These silicon-based computers were fundamentally different from the above-mentioned CNFET-based circuits in several key ways: they ran stored programs, they were programmable (meaning that they could execute a variety of computational tasks through proper sequencing of instructions without modifying the underlying hardware [14]) and they implemented synchronous digital systems incorporating combinational logic circuits interfaced with sequential elements such as latches and flip-flops [15].

It is well known that substantial imperfections inherent in CNT technology are the main obstacles to the demonstration of robust and complex CNFET circuits [16]. These include mis-positioned and metallic CNTs. Mis-positioned CNTs create stray conducting paths leading to incorrect logic functionality, whereas metallic CNTs have little or no bandgap, resulting in high leakage currents and incorrect logic functionality [17]. The imperfection-immune design paradigm, which combines circuit design techniques with CNT processing solutions, overcomes these problems [17, 18]. It enables us to demonstrate, for the first time, a complete CNT computer, realized entirely using CNFETs. Similar to the first silicon-based computers, our CNT computer, which is a synchronous digital system built entirely from CNFETs, runs stored programs and is programmable. Our CNT computer runs a basic operating system that performs multitasking, meaning that it can execute multiple programs concurrently (in an interleaved fashion). We demonstrate our CNT computer by concurrently executing a counting program and an integer-sorting program (coordinated by a basic multitasking operating system), and also by executing 20 different instructions from the commercial MIPS instruction set [19].

The CNT computer is a one-instruction-set computer, implementing the SUBNEG (subtract and branch if negative) instruction, inspired by early work in ref. 23. We implement the SUBNEG instruction because it is Turing complete and thus can be used to re-encode and perform any arbitrary instruction from any instruction-set architecture, albeit at the expense of execution time and memory space [21, 22]. The SUBNEG instruction is composed of three operands: two data addresses and a third partial next instruction address (the CNT computer itself completes the next instruction address, allowing for branching to different instruction addresses). The SUBNEG instruction subtracts the value of the data stored in the first data address from the value of the data stored in the second data address, and writes the result at the location of the second data address.

The next instruction address is calculated to be one of two possible branch locations, depending on whether the result of the subtraction is negative. The partial next instruction address given by the present SUBNEG instruction omits the least significant bit. The least significant bit is calculated by the CNT computer, on the basis of whether or not the result of the SUBNEG subtraction was negative. This bit, concatenated with the partial next instruction address given in the SUBNEG instruction, makes up the entire next instruction address. A diagram showing the SUBNEG implementation is shown in Fig. 1a.
Figure 1: (Click on the image to view higher resolution) SUBNEG and program implementation. (a) Flowchart showing the implementation of the SUBNEG instruction. (b) Sample program on CNT computer. Each row of the chart is a full SUBNEG instruction. It is composed of two data addresses and a partial next instruction address. The (omitted) least significant bit (LSB) of the next instruction address is calculated by the arithmetic unit of the CNT computer, and the most significant bit (MSB) of the next instruction address indicates the running program, either a counter or bubble-sort algorithm in this instance.

The CNFET computer is composed of 178 CNFETs, with each CNFET comprising ~10–200 CNTs, depending on relative sizing of the widths of the CNFETs. It follows the von Neumann architecture and the convention of most computers today, with the instruction and data memories implemented off-chip (these memories perform no other function than a single read or write in a clock cycle). The computer circuitry contains up to seven stages of cascaded logic, demonstrating our ability to cascade combinational logic stages, which is a necessity in realizing large digital systems. Transistor-level schematics of the subcomponents (D-latches and arithmetic units) are provided in ref. 24, along with a block-level diagram of the full CNT computer. Ref. 24 also provides details of the tasks performed by the CNT computer (instruction fetch, data fetch, arithmetic operation, and write-back), as well as details of its operating system.

The CNT-specific fabrication process is based on the process described in refs 18, 20, 23, 24. Importantly, the fabrication process is completely silicon-CMOS compatible owing to its low thermal budget (125 °C). We use standard cells for our subsystems, designed following the imperfection-immune methodology, which renders our circuits immune to both mis-positioned and metallic CNTs. Because this method ensures that the immunity to CNT imperfections is encapsulated entirely within standard cells, the fabrication is completely insensitive to the exact positioning of CNTs on the wafer and there is no per-unit customization, rendering our processing and design VLSI (very large-scale integration) compatible. The entire CNT computer is fabricated completely within a die on a single wafer. Each die contains five CNT computers, and each wafer contains 197 dies. There is no customization of any sort after circuit fabrication: all of the CNFETs and interconnects are predetermined during design, and there is no post-fabrication selection, configuration or fine-tuning of functional CNFETs. Just like any von Neumann computer, off-chip interconnects are used for connections to external memories. Our CNT-specific fabrication process and imperfection-immune design enables high yield and robust devices; the yield of the subsystems, such as D-latches, typically ranges from 80% to 90% (waveforms of 240 subsystems, including arithmetic logic units and D-latches, are shown in ref. 24). The primary causes of yield loss—particles resulting in broken lithography patterns, adhesion issues with metal lift-off and variations in machine etch rates—are consequences of the limitations of performing all fabrication steps in-house in an academic fabrication facility.

A scanning electron microscopy (SEM) image of a fabricated CNT computer is shown in Fig. 2. To demonstrate the working CNT computer, we perform multitasking with our basic operating system, concurrently running a counter program and an integer-sorting program (performing the bubble-sort algorithm). Although CNFET circuits promise improved speed [2, 4, 5], our computer runs at 1 kHz. This is not due to the limitations of the CNT technology or our design methodology, but instead is caused by capacitive loading introduced by the measurement setup, the 1-μm minimum lithographic feature size possible in our academic fabrication facility, and CNT density and contact resistance. The measured and expected outputs from the CNT computer (Fig. 2b) show correct operation. To demonstrate the flexibility and ability of the SUBNEG computer to implement any arbitrary instruction, we additionally perform 20 MIPS instructions (Fig. 2c) on the CNT computer. Although the CNT computer operates on single-bit data values, this is not a fundamental limitation, because any multibit computation can be performed with a single-bit computer through serial computation [20].

Figure 2: (Click on the image to view higher resolution) CNT computer results. (a) Scanning electron microscopy (SEM) image of an entire CNT computer. (b) Measured and expected output waveforms for a CNT computer, running the program shown in Fig. 1b. The exact match in logic value of the measured and expected output shows correct operation. As shown by the MSB (denoted [4]) of the next instruction address, the computer is switching between performing counting and sorting (bubble-sort algorithm). The running results of the counting and sorting are shown in the rows beneath the MSB of the next instruction address. (c) A list of the 20 MIPS instructions implemented and tested on the CNT computer.

We have reported a CNT computer fabricated entirely from CNFETs, and have demonstrated its ability to run programs, to run a basic operating system that performs multitasking, and to execute MIPS instructions. To achieve this we used the imperfection-immune design methodology and developed robust and repeatable CNT-specific design and processing. This demonstration confirms that CNFET-based circuits are a feasible and plausible emerging technology.

Acknowledgments: We acknowledge the support of the NSF (CISE), FCRP C2S2, FCRP FENA, STARNet SONIC and the Stanford Graduate Fellowship and the Hertz Foundation Fellowship (M.M.S.). We also acknowledge Z. Bao, A. Lin, H. (D.) Lin, M. Rosenblum, and J. Zhang for their advice and collaborations.

References:
[1] Aaron D. Franklin, Mathieu Luisier, Shu-Jen Han, George Tulevski, Chris M. Breslin, Lynne Gignac, Mark S. Lundstrom, Wilfried Haensch. "Sub-10 nm carbon nanotube transistor". Nano Letters, 12, 758–762 (2012). Abstract.
[2] Lan Wei, D.J. Frank, L. Chang, H.-S.P. Wong. "A non-iterative compact model for carbon nanotube FETs incorporating source exhaustion effects" in Proc. 2009 IEEE Intl Electron Devices Meeting 917–920 (2009). Abstract.
[3] L. Chang in Short Course IEEE Intl Electron Devices Meeting (IEEE, 2012).
[4] D.E. Nikonov, & I.A. Young, "Uniform methodology for benchmarking beyond-CMOS logic devices" in Proc. 2012 IEEE Intl Electron Devices Meeting 24–25 (2012). Abstract.
[5] Jie Deng, N. Patil, Koungmin Ryu, A. Badmaev, Zhou Chongwu, S. Mitra, H.-S.P. Wong, "Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections" in Proc. 2007 IEEE Intl Solid State Circuits Conf. 70–78 (IEEE, 2007). Abstract.
[6] Suio Iijima,  "Helical microtubules of graphitic carbon". Nature, 354, 56–58 (1991). Abstract.
[7] R. Martel, T. Schmidt, H. R. Shea, T. Hertel, Ph. Avouris. "Single-and multi-wall carbon nanotube field-effect transistors". Applied Physics Letters, 73, 2447 (1998). Abstract.
[8] Sander J. Tans, Alwin R. M. Verschueren, Cees Dekker, "Room-temperature transistor based on a single carbon nanotube". Nature, 393, 49–52 (1998). Abstract.
[9] Zhihong Chen, Joerg Appenzeller, Yu-Ming Lin, Jennifer Sippel-Oakley, Andrew G. Rinzler, Jinyao Tang, Shalom J. Wind, Paul M. Solomon, Phaedon Avouris. "An integrated logic circuit assembled on a single carbon nanotube". Science, 311, 1735 (2006). Abstract.
[10] Qing Cao, Hoon-sik Kim, Ninad Pimparkar, Jaydeep P. Kulkarni, Congjun Wang, Moonsub Shim, Kaushik Roy, Muhammad A. Alam, John A. Rogers. "Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates". Nature, 454, 495–500 (2008). Abstract.
[11] N. Patil, A. Lin, E.R. Myers, H.-S. P. Wong, S. Mitra, in Proc. Symp. VLSI Tech. 205–206. (2008).
[12] N. Patil, A. Lin, Jie Zhang, Hai Wei, K. Anderson, H.-S.P. Wong, S. Mitra. "Scalable carbon nanotube computational and storage circuits immune to metallic and mis-positioned carbon nanotubes". IEEE Transactions on NanoTechnology, 10, 744–750 (2011). Abstract.
[13] M. Shulaker, et al. in Proc. 2013 IEEE Intl Solid State Circuits Conf. 112–113 (IEEE, 2013).
[14] J. von Neumann, "First draft of a report on the EDVAC". IEEE Annals of the History of Computing, 15, 27–75 (1993). Abstract.
[15] Edward J. McCluskey, "Logic Design Principles with Emphasis on Testable Semicustom Circuits" (Prentice-Hall, 1986).
[16] Qing Cao, Shu-jen Han, George S. Tulevski, Yu Zhu, Darsen D. Lu, Wilfried Haensch, "Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics". Nature Nanotechnology, 8, 180–186 (2013). Abstract.
[17] Jie Zhang, A. Lin, N. Patil, Wei Hai, Wei Lan, H.-S.P. Wong, S. Mitra."Carbon Nanotube Robust digital VLSI". IEEE Transactions on CAD, 31, 453–471 (2012) . Abstract.
[18] Nishant Patil, "Design and Fabrication of Imperfection-Immune Carbon Nanotube Digital VLSI Circuits". PhD thesis, Stanford Univ. (2010). Full Thesis.
[19] J. L. Hennessy, D. A. Patterson, "Computer Architecture: A Quantitative Approach" (Kaufmann, 1990).
[20] Albert Lin, "Carbon Nanotube Synthesis, Device Fabrication, and Circuit Design for Digital Logic Applications". PhD thesis, Stanford Univ. (2010). Link.
[21] Rolf Herken, ed. "The Universal Turing Machine: A Half-Century Survey" (Springer, 1995).
[22] Peter J. Nürnberg, Uffe K. Wiil, David L. Hicks, "A grand unified theory for structural computing". Metainformatics, 3002, 1–16 (2004). Abstract.
[23] Max M. Shulaker, Hai Wei, Nishant Patil, J. Provine, Hong-Yu Chen, H.-S. P. Wong, Subhasish Mitra, "Linear increases in carbon nanotube density through multiple transfer technique". Nano Letters, 11, 1881–1886 (2011). Abstract.
[24] Max M. Shulaker, Gage Hills, Nishant Patil, Hai Wei, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra. "Carbon Nanotube computer". Nature, 501, 526–530 (2013). Abstract.

Labels:


0 Comments:

Post a Comment

Links to this post:

Create a Link